/* Copyright (C) 2008-2020 Allegro DVT2.  All rights reserved. */
#pragma once

#include "EncRegisterDefs.h"

AL_DEFINE_ZONE_ARRAY(AL_ENC1_CMD,
                     AL_ZONE(AL_ENC1_CMD_BANK_OFFSET, 0x000, 27),
                     AL_ZONE(AL_ENC1_CMD_BANK_OFFSET, 0x080, 26),
                     AL_ZONE(AL_ENC1_CMD_BANK_OFFSET, 0x180, 24),
                     )

AL_DEFINE_ZONE_ARRAY(AL_ENC2_CMD,
                     /* Entropy avc commands (Expected to be the first zone) */
                     AL_ZONE(AL_ENC2_CMD_BANK_OFFSET, 0x06C, 5),
                     /* Intermediate buffer addresses */
                     AL_ZONE(AL_ENC2_CMD_BANK_OFFSET, 0x0E8, 6),
                     )

#define NUM_STATUS 29

/* Some of the registers that were in Enc2 became Enc1. */
AL_DEFINE_ZONE_ARRAY(AL_ENC1_STATUS,
                     AL_ZONE(AL_ENC1_STATUS_BANK_OFFSET, 0x104, NUM_STATUS),
                     )

AL_DEFINE_ZONE_ARRAY(AL_ENC2_STATUS,
                     AL_ZONE_HACK(AL_ENC2_STATUS_BANK_OFFSET, 0x178, 0x1E4, 2),
                     )

AL_DEFINE_ZONE_ARRAY(AL_ENCJPEG_CMD,
                     AL_ZONE(AL_ENCJPEG_CMD_BANK_OFFSET, 0x000, 11),
                     )

AL_DEFINE_ZONE_ARRAY(AL_ENCJPEG_STATUS,
                     AL_ZONE(AL_ENCJPEG_STATUS_BANK_OFFSET, 0x030, 3),
                     )

/* Enc1 and Enc2 clocks are one and the same in versions before V200. */
AL_DEFINE_CMDTOP_REG32(Enc1ClockStatus, AL_ENC1_CMD_BANK_OFFSET, 0x1F4, 1, 16, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc1ClockCommand, AL_ENC1_CMD_BANK_OFFSET, 0x1F4, 2, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2ClockStatus, AL_ENC2_CMD_BANK_OFFSET, 0x1F4, 1, 16, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2ClockCommand, AL_ENC2_CMD_BANK_OFFSET, 0x1F4, 2, 0, uint8_t)

AL_DEFINE_TOP_REG32(EncResetCommonTop, 0x010, 1, 12, uint8_t)
AL_DEFINE_CORE_ADDR(Enc1CommandListAddress, 0x1E0)
AL_DEFINE_CORE_ADDR(Enc2CommandListAddress, 0x1E0)
AL_DEFINE_CMDTOP_REG32(Enc1Start, AL_ENC1_CMD_BANK_OFFSET, 0x1E4, 2, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2Start, AL_ENC2_CMD_BANK_OFFSET, 0x1E4, 2, 2, uint8_t)

/* point to the same register as the V120 and the Gen1 only have one performance meter
 * for both enc1 and enc2 */
AL_DEFINE_CMDTOP_REG32(Enc1PerformanceMeter, AL_ENC1_CMD_BANK_OFFSET, 0x1E8, 32, 0, uint32_t)
AL_DEFINE_CMDTOP_REG32(Enc2PerformanceMeter, AL_ENC1_CMD_BANK_OFFSET, 0x1E8, 32, 0, uint32_t)

AL_DEFINE_CMDTOP_REG32(Enc1Reset, AL_ENC1_CMD_BANK_OFFSET, 0x1F0, 1, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2Reset, AL_ENC2_CMD_BANK_OFFSET, 0x1F0, 1, 1, uint8_t)
AL_DEFINE_CMDTOP_REG32(ResetTopCore, AL_ENC1_CMD_BANK_OFFSET, 0x1F0, 1, 2, uint8_t)

AL_DEFINE_TOP_REG32(EncReadBandwidthStatus0, 0x0110, 32, 0, uint32_t)
AL_DEFINE_TOP_REG32(EncReadBandwidthStatus1, 0x0114, 32, 0, uint32_t)
AL_DEFINE_TOP_REG32(EncWriteBandwidthStatus0, 0x0118, 32, 0, uint32_t)
AL_DEFINE_TOP_REG32(EncWriteBandwidthStatus1, 0x011C, 32, 0, uint32_t)
AL_DEFINE_TOP_REG32(EncBandwidthTimeWindow, 0x104, 32, 0, uint32_t)

/* We use the Enc1ClockStatus and Enc1ClockCommand for the jpeg too */
AL_DEFINE_CMDTOP_REG32(JpegClockStatus, AL_ENC1_CMD_BANK_OFFSET, 0x1F4, 1, 16, uint8_t)
AL_DEFINE_CMDTOP_REG32(JpegClockCommand, AL_ENC1_CMD_BANK_OFFSET, 0x1F4, 2, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(JpegReset, AL_ENCJPEG_CMD_BANK_OFFSET, 0x01F0, 1, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(JpegStart, AL_ENCJPEG_CMD_BANK_OFFSET, 0x01E4, 1, 0, uint8_t)

#define AL_ENC_IRQ_EN_ADDR 0x14
#define AL_ENC_IRQ_ADDR 0x18
AL_DEFINE_TOP_ADDR(EncIrqEnable, AL_ENC_IRQ_EN_ADDR)
AL_DEFINE_TOP_MULTICORE_REG32(Enc1IrqEnable, AL_ENC_IRQ_EN_ADDR, 1, 0, 0, 0x04, uint8_t)
AL_DEFINE_TOP_MULTICORE_REG32(Enc2IrqEnable, AL_ENC_IRQ_EN_ADDR, 1, 2, 0, 0x04, uint8_t)
AL_DEFINE_TOP_ADDR(EncIrq, AL_ENC_IRQ_ADDR)
AL_DEFINE_TOP_MULTICORE_REG32(Enc1Irq, AL_ENC_IRQ_ADDR, 1, 0, 0, 0x04, uint8_t)
AL_DEFINE_TOP_MULTICORE_REG32(Enc2Irq, AL_ENC_IRQ_ADDR, 1, 2, 0, 0x04, uint8_t)

AL_DEFINE_TOP_REG32(EncIrqWDTEnable, AL_ENC_IRQ_EN_ADDR, 1, 31, uint8_t)
AL_DEFINE_TOP_REG32(EncIrqWDT, AL_ENC_IRQ_ADDR, 1, 31, uint8_t)

AL_DEFINE_TOP_MULTICORE_REG32(EncIrqJpegEnable, AL_ENC_IRQ_EN_ADDR, 1, 0, 0, 0x04, uint8_t)
AL_DEFINE_TOP_MULTICORE_REG32(EncIrqJpeg, AL_ENC_IRQ_ADDR, 1, 0, 0, 0x04, uint8_t)

AL_DEFINE_TOP_REG32(EncWatchdogControl, 0x0028, 2, 0, uint8_t)
AL_DEFINE_TOP_REG32(EncWatchdogStatus, 0x0028, 2, 16, uint8_t)
AL_DEFINE_TOP_REG32(EncWatchdogTimeoutValue, 0x002C, 32, 0, uint32_t)

AL_DEFINE_CMDTOP_REG32(Enc1RunFrame, AL_ENC1_CMD_BANK_OFFSET, 0x01F8, 1, 1, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc1RunSlice, AL_ENC1_CMD_BANK_OFFSET, 0x01F8, 1, 0, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2RunFrame, AL_ENC2_CMD_BANK_OFFSET, 0x01F8, 1, 4, uint8_t)
AL_DEFINE_CMDTOP_REG32(Enc2RunSlice, AL_ENC2_CMD_BANK_OFFSET, 0x01F8, 1, 3, uint8_t)
AL_DEFINE_CMDTOP_REG32(JpegRunFrame, AL_ENCJPEG_CMD_BANK_OFFSET, 0x01F8, 1, 1, uint8_t)

// DEFINING COMMAND AND STATUS:
AL_DEFINE_CMD_REG32U(Enc1IsLastCommand, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2IsLastCommand, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LowlatIrqEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2LowlatIrqEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1Standard, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32S(Enc1MaxCuSize, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 3, 24, int8_t)
AL_DEFINE_CMD_REG32S(Enc1MinCuSize, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 3, 20, int8_t)
AL_DEFINE_CMD_REG32U(Enc1MaxTuSize, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 2, 10, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1MinTuSize, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 2, 8, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1MaxTransfoDepthInter, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 3, 4, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1MaxTransfoDepthIntra, AL_ENC1_CMD_BANK_OFFSET, 0x0000, 3, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1BitDepthPcmChroma, AL_ENC1_CMD_BANK_OFFSET, 0x0004, 4, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1BitDepthPcmLuma, AL_ENC1_CMD_BANK_OFFSET, 0x0004, 4, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1PictureHeight, AL_ENC1_CMD_BANK_OFFSET, 0x0004, 11, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1PictureWidth, AL_ENC1_CMD_BANK_OFFSET, 0x0004, 11, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1TransfoSkipEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TemporalMvpEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1IntraPcmEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1IntraDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 26, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ColocatedFromL0, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 23, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ShowColocated, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 23, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ChromaMode, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 2, 20, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1BitDepthChroma, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 2, 18, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1BitDepthLuma, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 2, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RefRecCompressionEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 15, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1GlobalMotionVectorEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 14, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1QpTable16x16Enable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 13, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1AvcEntropySyncEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 11, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1AvcEntropyMode, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 10, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CabacInit, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 2, 8, uint8_t)

/* low freq and double ref are exclusive features. No IP version has both features*/

AL_DEFINE_CMD_REG32U(Enc1MaxNumMergeCandidate, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 3, 4, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SrcCompressionEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 1, 3, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CuQpDeltaDepth, AL_ENC1_CMD_BANK_OFFSET, 0x0008, 3, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1DependentSlice, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1FrameSkip, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SliceType, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileProcessing, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1WavefrontProcessing, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 26, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CostChromaMode, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SliceQp, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 8, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HighFreqEnable, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 1, 15, uint8_t)
AL_DEFINE_CMD_REG32S(Enc1SliceCrQpOffset, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 5, 8, int8_t)
AL_DEFINE_CMD_REG32S(Enc1SliceCbQpOffset, AL_ENC1_CMD_BANK_OFFSET, 0x000C, 5, 0, int8_t)
AL_DEFINE_CMD_REG32U(Enc1CoreId, AL_ENC1_CMD_BANK_OFFSET, 0x0010, 2, 20, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1DeblockingFilterAcrossSlices, AL_ENC1_CMD_BANK_OFFSET, 0x0010, 1, 19, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1DeblockingFilterDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0010, 1, 18, uint8_t)
AL_DEFINE_CMD_REG32S(Enc1BetaOffset, AL_ENC1_CMD_BANK_OFFSET, 0x0010, 6, 8, int8_t)
AL_DEFINE_CMD_REG32S(Enc1TcOffset, AL_ENC1_CMD_BANK_OFFSET, 0x0010, 5, 0, int8_t)
AL_DEFINE_CMD_REG32U(Enc1NumRefIndexL1, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 4, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1NumRefIndexL0, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 4, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LongTermRefL1, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 1, 23, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LongTermRefL0, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 1, 22, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1FirstLcuY, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1FirstAddrX, AL_ENC1_CMD_BANK_OFFSET, 0x0014, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1RefIndexL1, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 4, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RefIndexL0, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 4, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LongTermRefIndex0L1, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 1, 23, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LongTermRefIndex0L0, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 1, 22, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LastLcuY, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1AvailableRefB, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 1, 11, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1AvailableRefA, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 1, 10, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LastAddrX, AL_ENC1_CMD_BANK_OFFSET, 0x0018, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1DeblockingFilterAcrossTiles, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileNeighbourAvailability_E, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileNeighbourAvailability_D, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileNeighbourAvailability_C, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 26, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileNeighbourAvailability_B, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 25, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileNeighbourAvailability_A, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 1, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileHeight, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1TileWidth, AL_ENC1_CMD_BANK_OFFSET, 0x001C, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1MeVerticalRange_m1, AL_ENC1_CMD_BANK_OFFSET, 0x0020, 3, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1FixPredictor, AL_ENC1_CMD_BANK_OFFSET, 0x0020, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1MeHorizontalRange_m1, AL_ENC1_CMD_BANK_OFFSET, 0x0020, 3, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TileOriginY, AL_ENC1_CMD_BANK_OFFSET, 0x0020, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1TileOriginX, AL_ENC1_CMD_BANK_OFFSET, 0x0020, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1SclLoad, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SclEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LambdaLoad, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 29, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LambdaEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1AutoQpLoad, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1AutoQpEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 26, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1QpLoad, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 25, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RelativeQpEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1VectorsOutDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 23, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RecOutDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 22, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1WeightedPred, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 20, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ConstrainedIntraPred, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 19, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1StrongIntraSmooth, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 18, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LoopFilterPcmDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 17, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ReferencePictureFlag, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 15, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1LongTermColocL1, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 1, 11, uint8_t)
AL_DEFINE_CMD_REG32S(Enc1CrQpOffset, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 5, 5, int8_t)
AL_DEFINE_CMD_REG32S(Enc1CbQpOffset, AL_ENC1_CMD_BANK_OFFSET, 0x0024, 5, 0, int8_t)
AL_DEFINE_CMD_REG32U(Enc1L2CacheCapThreshold, AL_ENC1_CMD_BANK_OFFSET, 0x0028, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1BitsPerLcuThreshold, AL_ENC1_CMD_BANK_OFFSET, 0x0028, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1SyncRight, AL_ENC1_CMD_BANK_OFFSET, 0x002C, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SyncLeft, AL_ENC1_CMD_BANK_OFFSET, 0x002C, 1, 30, uint8_t)

AL_DEFINE_TOP_MULTICORE_REG32(Enc1MaxBurstSize, 0x0034, 2, 0, 0, 0, uint8_t)
AL_DEFINE_REMOVED_GET_REG32(Enc1MaxBurstSize, uint8_t)
AL_DEFINE_REMOVED_SET_REG32(Enc1MaxBurstSize, uint8_t)

AL_DEFINE_CMD_REG32U(Enc1NbCores, AL_ENC1_CMD_BANK_OFFSET, 0x002C, 2, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CoreColumnWidth, AL_ENC1_CMD_BANK_OFFSET, 0x002C, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1CoreColumnOffset, AL_ENC1_CMD_BANK_OFFSET, 0x002C, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1CurrentPoc, AL_ENC1_CMD_BANK_OFFSET, 0x0030, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RefAPoc, AL_ENC1_CMD_BANK_OFFSET, 0x0034, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RefBPoc, AL_ENC1_CMD_BANK_OFFSET, 0x0038, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1ColocatedPoc, AL_ENC1_CMD_BANK_OFFSET, 0x003C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1ColocatedRefAPoc, AL_ENC1_CMD_BANK_OFFSET, 0x0040, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1ColocatedRefBPoc, AL_ENC1_CMD_BANK_OFFSET, 0x0044, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1L2CacheEnable, AL_ENC1_CMD_BANK_OFFSET, 0x0048, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1ForceMvClip, AL_ENC1_CMD_BANK_OFFSET, 0x0048, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1L2CacheTileHeight, AL_ENC1_CMD_BANK_OFFSET, 0x0048, 4, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1VerticalMvRange, AL_ENC1_CMD_BANK_OFFSET, 0x0048, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1HorizontalMvRange, AL_ENC1_CMD_BANK_OFFSET, 0x0048, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1CacheTileXMax, AL_ENC1_CMD_BANK_OFFSET, 0x004C, 8, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CacheTileXMin, AL_ENC1_CMD_BANK_OFFSET, 0x004C, 8, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1CacheOffset, AL_ENC1_CMD_BANK_OFFSET, 0x004C, 16, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcLoadParameters, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcLoadContext, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcStoreContext, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 29, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcPreventBitOverflow, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcPreventBinOverflow, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 27, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcLoadStoreBufLevel, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 1, 26, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcPreventBinThreshold, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 8, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcLcuPerGroup, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 10, 6, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcGroupPerLcuRow, AL_ENC1_CMD_BANK_OFFSET, 0x0050, 6, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSyncRightMode, AL_ENC1_CMD_BANK_OFFSET, 0x0054, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSyncLeftMode, AL_ENC1_CMD_BANK_OFFSET, 0x0054, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcCoreId, AL_ENC1_CMD_BANK_OFFSET, 0x0054, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcTargetSize, AL_ENC1_CMD_BANK_OFFSET, 0x0054, 24, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcStreamBufferSize, AL_ENC1_CMD_BANK_OFFSET, 0x0058, 8, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcBitPerGroup, AL_ENC1_CMD_BANK_OFFSET, 0x0058, 24, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSceneChangeMinQp, AL_ENC1_CMD_BANK_OFFSET, 0x005C, 6, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSceneChangeSliceQp, AL_ENC1_CMD_BANK_OFFSET, 0x005C, 6, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcMaxQp, AL_ENC1_CMD_BANK_OFFSET, 0x005C, 6, 8, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcMinQp, AL_ENC1_CMD_BANK_OFFSET, 0x005C, 6, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcForceSceneChange, AL_ENC1_CMD_BANK_OFFSET, 0x0060, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSceneChangeDisable, AL_ENC1_CMD_BANK_OFFSET, 0x0060, 1, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSceneChangeThresholdGroup, AL_ENC1_CMD_BANK_OFFSET, 0x0060, 8, 20, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcSceneChangeThresholdBytes, AL_ENC1_CMD_BANK_OFFSET, 0x0060, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1HeaderMaxSize, AL_ENC1_CMD_BANK_OFFSET, 0x0064, 8, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1TargetSliceSize, AL_ENC1_CMD_BANK_OFFSET, 0x0064, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1GdrMode, AL_ENC1_CMD_BANK_OFFSET, 0x0068, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1GdrPosition, AL_ENC1_CMD_BANK_OFFSET, 0x0068, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc2BitDepthChroma, AL_ENC2_CMD_BANK_OFFSET, 0x006C, 2, 30, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2BitDepthLuma, AL_ENC2_CMD_BANK_OFFSET, 0x006C, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2HeaderSize, AL_ENC2_CMD_BANK_OFFSET, 0x006C, 10, 16, uint16_t)
AL_DEFINE_CMD_REG32U(Enc2BitsPerMbThreshold, AL_ENC2_CMD_BANK_OFFSET, 0x006C, 13, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc2SliceType, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 2, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2ChromaFormat, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 2, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2SliceQp, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 6, 16, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2AvcLowLatencySync, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 4, 12, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2EntropySync, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 1, 11, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2EntropyMode, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 1, 10, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2CabacInitIdc, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 2, 8, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2NbCores, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 2, 4, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2ConstrainedIntraPred, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 1, 3, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2Direct8x8Inference, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 1, 2, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2Transfo8x8Enable, AL_ENC2_CMD_BANK_OFFSET, 0x0070, 1, 1, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2NumRefIdxL1, AL_ENC2_CMD_BANK_OFFSET, 0x0074, 4, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2NumRefIdxL0, AL_ENC2_CMD_BANK_OFFSET, 0x0074, 4, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2PictureWidth, AL_ENC2_CMD_BANK_OFFSET, 0x0074, 10, 12, uint16_t)
AL_DEFINE_CMD_REG32U(Enc2FirstLcuY, AL_ENC2_CMD_BANK_OFFSET, 0x0074, 10, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc2SliceHeaderLength, AL_ENC2_CMD_BANK_OFFSET, 0x0078, 5, 24, uint8_t)
AL_DEFINE_CMD_REG32U(Enc2MacroblockNumber, AL_ENC2_CMD_BANK_OFFSET, 0x0078, 20, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2SliceHeader, AL_ENC2_CMD_BANK_OFFSET, 0x007C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1SrcLuma, AL_ENC1_CMD_BANK_OFFSET, 0x0080, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1SrcChroma, AL_ENC1_CMD_BANK_OFFSET, 0x0084, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Src10bitsFormat, AL_ENC1_CMD_BANK_OFFSET, 0x0088, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SrcFormat, AL_ENC1_CMD_BANK_OFFSET, 0x0088, 4, 27, uint8_t)

AL_DEFINE_CMD_REG32U(Enc1SrcPitchMap, AL_ENC1_CMD_BANK_OFFSET, 0x0088, 8, 19, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SrcPitch, AL_ENC1_CMD_BANK_OFFSET, 0x0088, 18, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1QpTable, AL_ENC1_CMD_BANK_OFFSET, 0x008C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RecLuma, AL_ENC1_CMD_BANK_OFFSET, 0x0090, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RecChroma, AL_ENC1_CMD_BANK_OFFSET, 0x0094, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Rec10bitsFormat, AL_ENC1_CMD_BANK_OFFSET, 0x0098, 1, 31, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RecFormat, AL_ENC1_CMD_BANK_OFFSET, 0x0098, 3, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RecPitchMap, AL_ENC1_CMD_BANK_OFFSET, 0x0098, 8, 19, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1RecPitch, AL_ENC1_CMD_BANK_OFFSET, 0x0098, 18, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1ScalingMatrix, AL_ENC1_CMD_BANK_OFFSET, 0x009C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref0Luma, AL_ENC1_CMD_BANK_OFFSET, 0x00A0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref0Chroma, AL_ENC1_CMD_BANK_OFFSET, 0x00A4, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref1Luma, AL_ENC1_CMD_BANK_OFFSET, 0x00A8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref1Chroma, AL_ENC1_CMD_BANK_OFFSET, 0x00AC, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1ColocatedVectors, AL_ENC1_CMD_BANK_OFFSET, 0x00B0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1HwrcContext, AL_ENC1_CMD_BANK_OFFSET, 0x00B4, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1MotionVectors, AL_ENC1_CMD_BANK_OFFSET, 0x00B8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1BitstreamSize, AL_ENC1_CMD_BANK_OFFSET, 0x00BC, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Bitstream, AL_ENC1_CMD_BANK_OFFSET, 0x00C0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1BitstreamMaxSize, AL_ENC1_CMD_BANK_OFFSET, 0x00C4, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1BitstreamOffset, AL_ENC1_CMD_BANK_OFFSET, 0x00C8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1BitstreamAvailableSize, AL_ENC1_CMD_BANK_OFFSET, 0x00CC, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1IntermediateBufferMapOut, AL_ENC1_CMD_BANK_OFFSET, 0x00D0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1IntermediateBufferDatOut, AL_ENC1_CMD_BANK_OFFSET, 0x00D4, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1IntermediateBufferDatOutOffset, AL_ENC1_CMD_BANK_OFFSET, 0x00D8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RecLumaMap, AL_ENC1_CMD_BANK_OFFSET, 0x00DC, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref0LumaMap, AL_ENC1_CMD_BANK_OFFSET, 0x00E0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref1LumaMap, AL_ENC1_CMD_BANK_OFFSET, 0x00E4, 32, 0, uint32_t)

AL_DEFINE_CMD_REG32U(Enc2AvcEntropyMapIn, AL_ENC2_CMD_BANK_OFFSET, 0x00E8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2AvcEntropyDatIn, AL_ENC2_CMD_BANK_OFFSET, 0x00EC, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2AvcEntropyBitstream, AL_ENC2_CMD_BANK_OFFSET, 0x00F0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2AvcEntropyBitstreamMaxSize, AL_ENC2_CMD_BANK_OFFSET, 0x00F4, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2AvcEntropyBitstreamOffset, AL_ENC2_CMD_BANK_OFFSET, 0x00F8, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc2AvcEntropyBitstreamAvailableSize, AL_ENC2_CMD_BANK_OFFSET, 0x00FC, 32, 0, uint32_t)

AL_DEFINE_CMD_REG32U(Enc1GmvL0_Y, AL_ENC1_CMD_BANK_OFFSET, 0x0180, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1GmvL0_X, AL_ENC1_CMD_BANK_OFFSET, 0x0180, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1GmvL1_Y, AL_ENC1_CMD_BANK_OFFSET, 0x0184, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(Enc1GmvL1_X, AL_ENC1_CMD_BANK_OFFSET, 0x0184, 16, 0, uint16_t)

AL_DEFINE_CMD_REG32U(Enc1SrcLumaMap, AL_ENC1_CMD_BANK_OFFSET, 0x0190, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1SrcChromaMap, AL_ENC1_CMD_BANK_OFFSET, 0x0194, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1RecChromaMap, AL_ENC1_CMD_BANK_OFFSET, 0x019C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref0ChromaMap, AL_ENC1_CMD_BANK_OFFSET, 0x01A0, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(Enc1Ref1ChromaMap, AL_ENC1_CMD_BANK_OFFSET, 0x01A4, 32, 0, uint32_t)

AL_DEFINE_CMD_REG32U(Enc1SrdInit, AL_ENC1_CMD_BANK_OFFSET, 0x01B8, 1, 28, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SrdThreshold, AL_ENC1_CMD_BANK_OFFSET, 0x01B8, 8, 0, uint8_t)
AL_DEFINE_CMD_REG32U(Enc1SrdBuffer, AL_ENC1_CMD_BANK_OFFSET, 0x01BC, 32, 0, uint32_t)

AL_DEFINE_STATUS_REG32U(EncLcuOverflow, AL_ENC1_STATUS_BANK_OFFSET, 0x0104, 1, 31, uint8_t)
AL_DEFINE_STATUS_REG32U(EncBufferOverflow, AL_ENC1_STATUS_BANK_OFFSET, 0x0104, 1, 30, uint8_t)
AL_DEFINE_STATUS_REG32U(EncBitstreamByteSize, AL_ENC1_STATUS_BANK_OFFSET, 0x0104, 30, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncBitstreamBinSize, AL_ENC1_STATUS_BANK_OFFSET, 0x0108, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncResidualBitSize, AL_ENC1_STATUS_BANK_OFFSET, 0x010C, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncResidual4x4, AL_ENC1_STATUS_BANK_OFFSET, 0x0110, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncIntra8x8, AL_ENC1_STATUS_BANK_OFFSET, 0x0114, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncSkipped8x8, AL_ENC1_STATUS_BANK_OFFSET, 0x011C, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncCodingUnit8x8, AL_ENC1_STATUS_BANK_OFFSET, 0x0120, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncCodingUnit16x16, AL_ENC1_STATUS_BANK_OFFSET, 0x0124, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncCodingUnit32x32, AL_ENC1_STATUS_BANK_OFFSET, 0x0128, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(EncVp9HeaderSize, AL_ENC1_STATUS_BANK_OFFSET, 0x012C, 16, 16, uint16_t)
AL_DEFINE_STATUS_REG32U(EncCodingUnit64x64, AL_ENC1_STATUS_BANK_OFFSET, 0x012C, 16, 0, uint16_t)
AL_DEFINE_STATUS_REG32U(Enc1ComplexitySum, AL_ENC1_STATUS_BANK_OFFSET, 0x0130, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1QpSum, AL_ENC1_STATUS_BANK_OFFSET, 0x0134, 28, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SliceNumber, AL_ENC1_STATUS_BANK_OFFSET, 0x0138, 16, 16, uint16_t)
AL_DEFINE_STATUS_REG32U(Enc1MaxQp, AL_ENC1_STATUS_BANK_OFFSET, 0x0138, 8, 8, uint8_t)
AL_DEFINE_STATUS_REG32U(Enc1MinQp, AL_ENC1_STATUS_BANK_OFFSET, 0x0138, 8, 0, uint8_t)
AL_DEFINE_STATUS_REG32U(Enc1ByteSize, AL_ENC1_STATUS_BANK_OFFSET, 0x013C, 32, 0, uint32_t)

AL_DEFINE_STATUS_REG32U(Enc1SumMvL0_X, AL_ENC1_STATUS_BANK_OFFSET, 0x0140, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SumMvL0_Y, AL_ENC1_STATUS_BANK_OFFSET, 0x0144, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SumMvL1_X, AL_ENC1_STATUS_BANK_OFFSET, 0x0148, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SumMvL1_Y, AL_ENC1_STATUS_BANK_OFFSET, 0x014C, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1NbMvL0, AL_ENC1_STATUS_BANK_OFFSET, 0x0150, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1NbMvL1, AL_ENC1_STATUS_BANK_OFFSET, 0x0154, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SsdLuma_MSB, AL_ENC1_STATUS_BANK_OFFSET, 0x0158, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SsdLuma_LSB, AL_ENC1_STATUS_BANK_OFFSET, 0x015C, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SsdChromaBR_MSB, AL_ENC1_STATUS_BANK_OFFSET, 0x0160, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1SsdChromaBR_LSB, AL_ENC1_STATUS_BANK_OFFSET, 0x0164, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1L2CacheMissY0, AL_ENC1_STATUS_BANK_OFFSET, 0x0170, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1L2CacheMissY1, AL_ENC1_STATUS_BANK_OFFSET, 0x0174, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1NumObtainedMode, AL_ENC1_STATUS_BANK_OFFSET, 0x0188, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(Enc1NumAllowedMode, AL_ENC1_STATUS_BANK_OFFSET, 0x018c, 32, 0, uint32_t)

/* These status are special in V120 because they don't have the same cmdlist
 * and registers offset. This is due to two factors: A lack of space in register banks
 * and a burst issue in the cmdlist */
AL_DEFINE_STATUS_HACK_REG32U(Enc2LcuOverflow, AL_ENC2_STATUS_BANK_OFFSET, 0x0178, 0x01E4, 1, 31, uint8_t)
AL_DEFINE_STATUS_HACK_REG32U(Enc2BufferOverflow, AL_ENC2_STATUS_BANK_OFFSET, 0x0178, 0x01E4, 1, 30, uint8_t)
AL_DEFINE_STATUS_HACK_REG32U(Enc2BitstreamByteSize, AL_ENC2_STATUS_BANK_OFFSET, 0x0178, 0x01E4, 30, 0, uint32_t)
AL_DEFINE_STATUS_HACK_REG32U(Enc2BitstreamBinSize, AL_ENC2_STATUS_BANK_OFFSET, 0x017C, 0x01E8, 32, 0, uint32_t)

AL_DEFINE_CMD_REG32U(JpegRestartInterval, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(JpegDensityUnit, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 2, 12, uint8_t)
AL_DEFINE_CMD_REG32U(JpegLosslessEnable, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 1, 9, uint8_t)
AL_DEFINE_CMD_REG32U(JpegLoadTables, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 1, 8, uint8_t)
AL_DEFINE_CMD_REG32U(JpegNbComponents, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 2, 4, uint8_t)
AL_DEFINE_CMD_REG32U(JpegChromaFormat, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0000, 2, 0, uint8_t)
AL_DEFINE_CMD_REG32U(JpegPictureWidth, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0004, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(JpegPictureHeight, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0004, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(JpegDensityX, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0008, 16, 16, uint16_t)
AL_DEFINE_CMD_REG32U(JpegDensityY, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0008, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(JpegPicturePitch, AL_ENCJPEG_CMD_BANK_OFFSET, 0x000C, 16, 0, uint16_t)
AL_DEFINE_CMD_REG32U(JpegSrcLuma, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0010, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegSrcChroma, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0014, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegTables, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0018, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegBitstream, AL_ENCJPEG_CMD_BANK_OFFSET, 0x001C, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegBitstreamMaxSize, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0020, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegBitstreamOffset, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0024, 32, 0, uint32_t)
AL_DEFINE_CMD_REG32U(JpegBitstreamAvailableSize, AL_ENCJPEG_CMD_BANK_OFFSET, 0x0028, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(JpegStatusSyntaxElements, AL_ENCJPEG_STATUS_BANK_OFFSET, 0x0030, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(JpegStatusBytes, AL_ENCJPEG_STATUS_BANK_OFFSET, 0x0034, 32, 0, uint32_t)
AL_DEFINE_STATUS_REG32U(JpegBitstreamException, AL_ENCJPEG_STATUS_BANK_OFFSET, 0x0038, 1, 1, uint8_t)

